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09/23/15 12:31

GRADE@ ESSDERC: 5 contributed papers, one Tutorial and a Workshop

The GRADE project continues to drive the state of the art in graphene RF devices and circuits in Europe. Five papers were presented in the week from September 14 to 18 in Graz, Austria at the European Solid-State Device Research Conference (ESSDERC), the premier device conference in Europe. The research in all 5 accepted papers on graphene transistors, technology and circuits were funded through the GRADE project. All papers from the Proceedings will become available in IEEE Xplore.

In addition to these papers, Dr. Fregonese from the University of Bordeaux lectured on compact modeling and circuit design with graphene field effect transistors in Monday’s Tutorial on “Novel Transistors – Beyond the Planar Silicon MOSFET”, organized by GRADE Coordinator Prof. Lemme. On Friday, Sep 18th, Dr. Passi from the University of Siegen lectured on “Graphene and Two-Dimensional (2D) Materials for Nanoelectronics” in the Workshop “New Materials for Nanoelectronics”, organized by the SINANO Institute.

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